Input voltage adaptive jitter for quasi-resonant control

ABSTRACT

A power converter includes a power switch controlling current flow in the power converter and a variable capacitance coupled in parallel to the power switch. The variable capacitance is configured to add a frequency jitter to the power converter.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 16/667,585, filed Oct. 29, 2019, entitled “CIRCUIT AND METHOD FOR JITTER GENERATION IN QUASI-RESONANT CONVERTER,” which claims priority to U.S. Provisional Patent Application No. 62/816,048, filed Mar. 8, 2019, entitled “CIRCUIT AND METHOD FOR JITTER GENERATION IN QUASI-RESONANT CONVERTER.” This application also claims priority to U.S. Provisional Patent Application No. 62/986,449, filed Mar. 6, 2020, entitled “INPUT VOLTAGE ADAPTIVE JITTER FOR QUASI-RESONANT CONTROL.” The content of all the above-listed applications is incorporated by reference in their entirety herein for all purposes.

BACKGROUND OF THE INVENTION

The present invention relates to switching mode power supplies. More particularly, the invention provides methods and apparatus for reducing electromagnetic interference (EMI) of switching mode power supplies.

Regulated power supplies are indispensable in modern electronics. For example, the power supply in a personal computer often needs to receive power input from various outlets. Desktop and laptop computers often have regulated power supplies on the motherboard to supply power to the CPU, memories, and periphery circuitry. Regulated power supplies are also used in a wide variety of applications, such as home appliances, automobiles, and portable chargers for mobile electronic devices, etc.

In general, a power supply can be regulated using a linear regulator or a switching mode controller. A linear regulator maintains the desired output voltage by dissipating excess power. In contrast, a switching mode controller rapidly switches a power transistor on and off with a variable duty cycle or variable frequency and provides an average output that is the desired output voltage.

In such a switched mode power supply system, a switch is connected to the primary winding of the transformer. In the switching power supplies, the power transistor switches on and off periodically to convert the primary current of the transformer to the secondary side. The stable output voltage will be obtained by regulating the duty cycle or frequency of the primary side switch. Magnetic energy is stored in the inductance of the primary winding when the switch is turned on, and the energy is transferred to the secondary winding when the switch is turned off. The energy transfer results in a current flowing through the secondary winding and the rectifying diode. When the energy transfer is completed, the current stops flowing through the diode. If the switching mode power supply, also referred to as the flyback converter, operates in discontinuous conduction mode (DCM), during the discontinuous time, a resonant waveform of substantially sinusoidal oscillation of decreasing amplitude appears at the secondary winding and across the power switch due to the built-in inductance and capacitance in the converter. After the discontinuous time, the power switch is turned on again in the next switching cycle.

In quasi-resonant (QR) switching, the controller waits for one of the valleys in the resonant waveform of the drain voltage and then turns on the power switch. Compared with the traditional continuous conduction mode (CCM) and discontinuous conduction mode (DCM) of operation in a flyback converter, quasi-resonant switching can reduce turn-on losses at the power switch, thus increasing efficiency and lowering device temperatures.

Compared with linear regulators, switching mode power supplies have the advantages of smaller size, higher efficiency and larger output power capability. On the other hand, they also have the disadvantages of greater noise, especially electromagnetic Interference (EMI) at the power transistor's switching frequency or its harmonics.

EMI is a critical issue in the design of a switching mode power supply. In order to reduce EMI, different frequency jittering techniques can be used. For example, switching frequencies may be varied by frequency modulation in order to spread out the electromagnetic radiation energy across a frequency range. One way to vary the switching frequency is to add a jitter component to the system clock. This technique helps reducing average EMI emission. However, implementing effective jittering can be difficult in a quasi-resonant (QR) converter, as explained further below.

BRIEF SUMMARY OF THE INVENTION

The inventor has recognized that, in a quasi-resonant (QR) converter, it is difficult to implement effective frequency jitter. Under discontinuous conduction mode (DCM), the flyback converter has an LC resonant waveform during the discontinuous time after the secondary side current is discharged. The QR operation turns on the power switch at a valley point of resonant voltage. The turn-on condition at a valley point of the resonant voltage can limit the switching frequencies of the flyback system and prevent the switching frequency to spread over a relatively large frequency range. As a result, the effectiveness of the jittering is limited.

This invention teaches a technique for introducing jitter in the switching frequency of a power converter. The power converter includes a power switch controlling the primary current flow, and a time-varying capacitance is coupled in parallel to the power switch. The time-varying capacitance adds a frequency jitter to the frequency of the converter.

This invention also teaches a power converter having a power switch controlling current flow in the power converter and a variable capacitance coupled in parallel to the power switch. The variable capacitance is configured to add a frequency jitter to the power converter. In some embodiments, the frequency jitter comprises a first portion that varies with an input voltage of the power converter and a second portion that is a time-varying function. The first portion that varies with an input voltage can reduce the switching loss of the power converter. In some embodiments, the variable capacitance comprises a transistor coupled in series with a capacitor.

As an example, this invention teaches a power converter that includes a transformer having a primary winding for coupling to an input voltage, a secondary winding providing an output voltage of the power converter, and a sensing circuit for providing a sensing signal, which monitors a resonant waveform of the power converter during discontinuous time. The power converter includes a power switch for coupling to the primary winding of the power converter to control a primary current flow, and a capacitor and a modulation switch coupled in parallel to the power switch.

The power converter can also include a control circuit that includes a power controller for turning on the power switch in response to the resonant waveform in the sensing signal during a discontinuous time, and a jitter controller for turning on the modulation switch in response to the resonant waveform in the sensing signal during the discontinuous time. The jitter controller varies a turn-on time of the modulation switch to add a frequency jitter to a switching frequency of the power converter. The frequency jitter can include a first portion that varies with the input voltage of the power converter and a second portion that is a time-varying function.

As another example, this invention teaches a method for controlling a power converter. The method includes turning on a power switch in response to a resonant waveform in a sensing signal during a discontinuous time of the power converter, wherein the power switch is coupled to a primary winding of the power converter to control a primary current flow. The method also includes adding a capacitance in parallel to the power switch during the discontinuous time, to vary an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the power converter. The method can add a capacitance in parallel to the power switch by turning on a modulation switch that is coupled in series with a capacitor, wherein the capacitor and the modulation switch are coupled in parallel with the power switch. The frequency jitter can include a first portion that varies with an input voltage of the power converter and a second portion that is a time-varying function.

The invention also teaches a power converter having a power switch controlling current flow in the power converter and a variable capacitance coupled in parallel to the power switch. The variable capacitance is configured to add a frequency jitter to the power converter. In some embodiments, the frequency jitter comprises a first portion that varies with an input voltage of the power converter and a second portion that is a time-varying function. In some embodiments, the variable capacitance comprises a transistor couple in series with a capacitor.

In another example, this invention teaches a method for controlling a quasi-resonant (QR) converter to reduce electromagnetic interference (EMI). The converter includes a power switch coupled to a primary winding of the converter to control a primary current flow, and a sensing signal monitoring the converter through an auxiliary winding. The method includes turning on the power switch at a valley point of a resonant waveform in the sensing signal during a discontinuous time of the converter for quasi-resonant (QR) operation. The method further includes adding a capacitance in parallel to the power switch at a peak point of the resonant waveform in the sensing signal during the discontinuous time, to vary an oscillation period of the resonant waveform, which leads to variations of the discontinuous time and changes the switching frequency of the converter. A modulation switch with a time-varying on-time can be used to control the duration of time in which the additional capacitance is in effect. For example, the time-varying duration can be a linear function of time to spread out the switching frequency across a relatively large frequency range.

In another example, this invention teaches a control circuit for a quasi-resonant (QR) converter. The control circuit includes a quasi-resonant controller for turning on a power switch at a valley point of a resonant waveform in a sensing signal during a discontinuous time of the converter. The power switch is coupled to a primary winding of the converter to control a primary current flow, and the sensing signal is monitoring the resonant waveform of the converter through an auxiliary winding. The control circuit also includes a jitter controller for adding a capacitance in parallel to the power switch at a peak point of the resonant waveform in the sensing signal during the discontinuous time. The jitter controller varies an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the converter.

In another example, this invention teaches a quasi-resonant (QR) converter. The converter includes a transformer having a primary winding for coupling to an external input voltage, a secondary winding providing an output voltage of the converter, and an auxiliary winding for providing a sensing signal of the converter. The converter also has a power switch for coupling to the primary winding of the converter to control a primary current flow, and a capacitor and a modulation switch coupled in parallel to the power switch, with the modulation switch coupled in series with the capacitor. The converter also has a control circuit that includes a quasi-resonant controller and a jitter controller. The quasi-resonant controller turns on the power switch at a valley point of a resonant waveform in the sensing signal during a discontinuous time. The jitter controller turns on the modulation switch at a peak point of the resonant waveform in the sensing signal during the discontinuous time. The jitter controller varies a turn-on time of the modulation switch to add a frequency jitter to a switching frequency of the converter.

In another example, this invention teaches a control circuit for a quasi-resonant (QR) converter. The control circuit includes a quasi-resonant controller for turning on a power switch at a valley point of a resonant waveform in a sensing signal during a discontinuous time of the converter, wherein the power switch is coupled to a primary winding of the converter to control a primary current flow, and the sensing signal monitors the resonant waveform of the converter through an auxiliary winding. The control circuit also includes a jitter controller for modulating a capacitance coupled in parallel to the power switch to vary an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the converter. The frequency jitter includes a first portion that varies with an input voltage of the converter and a second portion that is a time-varying function. In an embodiment, the jitter controller starts varying the oscillation period at a peak point of the resonant waveform in the sensing signal during the discontinuous time.

In another example, this invention teaches a method for controlling a quasi-resonant (QR) converter. The method includes turning on a power switch at a valley point of a resonant waveform in a sensing signal during a discontinuous time of the converter. The power switch is coupled to a primary winding of the converter to control a primary current flow, and the sensing signal monitors the resonant waveform of the converter through an auxiliary winding. The method also includes modulating a capacitance coupled in parallel to the power switch to vary an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the converter. The oscillation period includes an offset that varies with an input voltage of the converter and a time-varying dithering period. In an embodiment, the method also includes starting to vary the oscillation period at a peak point of the resonant waveform in the sensing signal during the discontinuous time.

Definitions

The terms used in this disclosure generally have their ordinary meanings in the art within the context of the invention. Certain terms are discussed below to provide additional guidance to the practitioners regarding the description of the invention. It will be appreciated that the same thing may be said in more than one way. Consequently, alternative language and synonyms may be used.

A power switch as used herein refers to a semiconductor switch, for example, a transistor, that is designed to handle high power levels.

A power MOSFET is a specific type of metal oxide semiconductor field-effect transistor (MOSFET) designed to handle significant power levels. An example of a power MOSFET for switching operations is called a double-diffused MOS or simply DMOS.

A body diode in a power MOSFET is formed when the body and source are coupled together, and the body diode is formed between drain and source. The diode is located between the drain (cathode) and the source (anode) of the MOSFET making it able to block current in only one direction.

A power converter is an electrical or electro-mechanical device for converting electrical energy, such as converting between AC and DC or changing the voltage, current, or frequency, or some combinations of these conversions. A power converter often includes voltage regulation.

A regulator or voltage regulator is a device for automatically maintaining a constant voltage level.

A switching regulator, or switch mode power supply (SMPS) is a power converter that uses an active device that switches on and off to maintain an average value of output. In contrast, a linear regulator is made to act like a variable resistor, continuously adjusting a voltage divider network to maintain a constant output voltage, and continually dissipating power.

Continuous conduction mode (CCM) is an operational mode of a power converter, in which the system turns on the primary side current before the secondary side current is stopped.

Discontinuous conduction mode (DCM) is an operational mode of a power converter, in which there exists a discontinuous time period, during which the current flow is stopped on both the primary side and the secondary side. The primary side is turned on again following the discontinuous time period.

Quasi-resonant (QR) mode is an operational mode of a power converter operating in discontinuous conduction mode (DCM), in which the primary side is turned on at a valley point of a resonant waveform during the discontinuous time period. Quasi-resonant operation can reduce switching loss of the power converter.

An operational amplifier (op-amp or opamp) refers to a DC-coupled high-gain electronic voltage amplifier with a differential input and, usually, a single-ended output. An operational amplifier can be characterized by a high input impedance and a low output impedance, and can be used to perform mathematical operations in analog circuits.

A voltage reference is an electronic device that ideally produces a fixed (constant) voltage irrespective of the loading on the device, power supply variations, temperature changes, and the passage of time.

A reference voltage is a voltage value that is used as a target for a comparison operation.

When the term “the same” is used to describe two quantities, it means that the values of two quantities are determined the same within measurement limitations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic diagram of a flyback converter that embodies certain aspects of this invention;

FIG. 2A is a simplified schematic diagram of part of flyback converter 100 of FIG. 1, and FIG. 2B shows waveform diagrams that illustrate a quasi-resonant operation of the converter that embodies certain aspects of this invention;

FIG. 3 is a waveform diagram that illustrates a jitter in a quasi-resonant operation of the converter that embodies certain aspects of this invention;

FIGS. 4A-4D illustrate an example of providing jitter to a converter that that embodies certain aspects of this invention;

FIG. 5A illustrates the waveforms for the QR converter in which the jitter time t_(jitter) is near zero, and the oscillation period for a resonant waveform is T_(QR), as described above;

FIG. 5B illustrates the waveforms for the QR converter in which the jitter time t_(jitter) is at the maximum, t_(jitterMax), and the oscillation period for a resonant waveform is T_(QR1), as described above;

FIGS. 6-10 are schematic or waveform diagrams illustrating the structures and functions of various components in the control circuit in a converter that embody certain aspects of this invention;

FIG. 6 shows schematic and waveform diagrams illustrating the structures and functions of a valley detector and a peak detector in the control circuit in a converter that embodies certain aspects of this invention;

FIG. 7A is a simplified schematic diagram illustrating a jitter controller, and FIG. 7B illustrates a waveform diagram that describes the operation of the jitter controller that embodies certain aspects of this invention;

FIG. 8A is a simplified schematic diagram illustrating a blanking time generation circuit, and FIG. 8B illustrates a waveform diagram that describes the operation of the blanking time generation circuit that embodies certain aspects of this invention;

FIG. 9 is a simplified schematic diagram illustrating a first example of a quasi-resonant controller that embodies certain aspects of this invention;

FIG. 10 is a simplified schematic diagram illustrating a second example of a quasi-resonant controller that embodies certain aspects of this invention;

FIG. 11A is a simplified schematic diagram illustrating a quasi-resonant (QR) converter with jitter that embodies certain aspects of this invention;

FIG. 11B is a waveform diagram illustrating the operation of the quasi-resonant (QR) converter with jitter of FIG. 11B that embodies certain aspects of this invention;

FIG. 12A is a simplified schematic diagram illustrating a quasi-resonant (QR) converter with jitter that embodies certain aspects of this invention;

FIG. 12B is a waveform diagram illustrating the operation of the quasi-resonant (QR) converter with jitter of FIG. 12A that embodies certain aspects of this invention;

FIG. 13 is a simplified flowchart that illustrates a method for controlling a quasi-resonant (QR) converter that embodies certain aspects of this invention;

FIG. 14 is a simplified schematic diagram illustrating a power converter with jitter that embodies certain aspects of this invention;

FIG. 15 illustrates the waveforms for the power converter of FIG. 14 that embodies certain aspects of this invention;

FIG. 16 illustrates a method of providing a range of frequency jitter to a converter that that embodies certain aspects of this invention;

FIG. 17 illustrates waveforms for a converter that embodies certain aspects of this invention;

FIG. 18 illustrates waveforms for a converter that embodies certain aspects of this invention;

FIGS. 19A-19C illustrate waveforms for the converter that embodies certain aspects of this invention;

FIG. 20 illustrates waveforms for a converter that embodies certain aspects of this invention;

FIG. 21 is a simplified schematic diagram of a flyback converter that embodies certain aspects of this invention;

FIG. 22 shows a simplified schematic and waveform diagrams illustrating the structures and functions of a valley detector and a peak detector in the control circuit in a converter that embodies certain aspects of this invention;

FIG. 23 shows a simplified schematic for detecting the input voltage that embodies certain aspects of this invention;

FIG. 24 is a simplified schematic diagram illustrating a jitter controller that embodies certain aspects of this invention;

FIG. 25 illustrates a waveform diagram that describes the operation of the jitter controller of FIG. 24 that embodies certain aspects of this invention;

FIG. 26 is a simplified schematic diagram illustrating a blanking time generation circuit and waveform diagram that embodies certain aspects of this invention;

FIG. 27 is a simplified schematic diagram illustrating an example of a power controller that embodies certain aspects of this invention; and

FIG. 28 is a simplified flowchart that illustrates a method for controlling a power converter that embodies certain aspects of this invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a simplified schematic diagram of a flyback converter that embodies certain aspects of this invention. Flyback converter 100 includes a transformer 102, which includes a primary winding 141 for coupling to an input voltage V_(in) and a secondary winding 142 for providing the output voltage V_(out) through a rectifying diode 120 and a capacitor 119. A current in the rectifying diode is I_(D). Transformer 102 also has an auxiliary winding 143 for providing a sensing signal DMEG monitoring a resonant waveform of the converter during a discontinuous time. Auxiliary winding 143 also provides a voltage V_(cc), which can be used as a power supply for the support circuitry, such as a control circuit. In FIG. 1, Vp denotes the voltage at the primary winding, Vs denotes the voltage at the secondary winding, and Va denotes the voltage at the auxiliary winding. In FIG. 1, L_(m) represents the inductance of the primary winding, and N represents the ratio of coil turns in the primary winding to the secondary winding. C_(oss) represents the capacitance associated with primary switch 101, including the capacitance from the body diode. Vds represents the drain-source voltage across the primary switch.

Converter 100 includes a control circuit 150. Power supply 100 also includes a power switch 101 (also designated as Q_(L)) coupled to primary winding 141 and control circuit 150 for receiving a control signal to turn on and off power switch 101 to control the primary current through primary winding 141 in order to regulate output voltage V_(OUT). In FIG. 1, power switch 101 is shown as a MOSFET power transistor. In the embodiment of FIG. 1, control circuit 150 can receive its operating power from V_(cc) provided by the auxiliary winding. Control circuit 150 can also receive sensing signal DMEG from auxiliary winding 143. Control circuit 150 can also receive a current sense signal Vcs representative of the primary current through a current sense resistor 116 with a resistance Rcs. Control circuit 150 provides a control signal Drive to control power switch 101. Control circuit 150 turns on the power switch 101 based on information provided by the sensing signal DMEG and turns off the power 101 based on information provided by the current sense signal Vcs.

As shown in FIG. 1, converter 100 also has a modulation capacitor 130 (also designated as C_(sn)) and a modulation switch 131 (also designated as Q_(M)) coupled in parallel to power switch 101. In this arrangement, modulation switch 131 is coupled in series with capacitor 130. Control circuit 150 includes a valley detector 151 for detecting valley points in the resonant waveform in the sensing signal DMEG during the discontinuous time of converter 100. Control circuit 150 also includes a peak detector 152 for detecting peak points in the resonant waveform in the sensing signal during the discontinuous time. Control circuit 150 also includes a quasi-resonant (QR) controller 153 for turning on the power switch 101 at a valley point of a resonant waveform in the sensing signal during a discontinuous time. Control circuit 150 further includes a jitter controller 154 for turning on the modulation switch 131 at a peak point of the resonant waveform in the sensing signal during the discontinuous time. Control circuit 150 also includes an oscillator OSC 155, which provides a T_(FMAX) signal to jitter controller 154. In addition to the T_(FMAX) signal, jitter controller 154 also receives a Ppulse signal from peak detector 152, and provides a Mod_Off signal to QR controller 153. QR controller 153 also receives a Vpulse signal from valley detector 151. Control circuit 150 also includes a flipflop 156 that outputs the Drive signal.

As explained in detail below, the jitter controller 154 varies a turn-on time of the modulation switch 131 to add a frequency jitter to the switching frequency of the converter. The waveform of Vds is mirrored to the auxiliary winding and detected by a peak detector and a valley detector. The jitter controller determines the target peak count to turn on Q_(M) and linearly modulates the on time of Q_(M). After Q_(M) is turned off, the QR controller is enabled by the jitter controller to wait for proper valley count and turn on Q_(L) at the valley of Vds.

FIG. 2A is a simplified schematic diagram of part of flyback converter 100 of FIG. 1, and FIG. 2B shows waveform diagrams that illustrate a quasi-resonant operation of the converter that embodies certain aspects of this invention. In FIG. 2B, the following waveforms are shown over a switch cycle T of the converter. The first waveform “Drive” shows the control signal Drive applied to the primary switch 101. The second waveform “Vds” shows the drain-to-source voltage Vds of the primary switch, which can be reflected in the sensing signal DMEG of FIG. 1. The third waveform shows the primary current I_(PRI) feeding into the primary side of the transformer. The fourth waveform shows the secondary current I_(SEC) flowing out of the secondary side of the transformer. As can be seen in FIG. 2B, the primary switch is turned on during time period t_(ON), and turned off during time period t_(OFF). During time period t_(ON), the primary current flows through the primary switch. The secondary current flows during a first portion of time period t_(OFF). Time period t_(DIS) is a discontinuous time, during which both the primary current and the secondary current are off. During discontinuous time t_(DIS), a resonant waveform 220 exists in the waveforms of Vds, as well as DMEG. In the example of FIG. 2B, resonant waveform 220 is shown to have three peak points 221, 223, and 225 and three valley points 222, 224, and 226, marked by K=1, K=2, and K=3. In a quasi-resonant operation, the quasi-resonant controller 153 in FIG. 1 turns on the power switch at a valley point of a resonant waveform in the sensing signal during the discontinuous time. In FIG. 2B, the primary switch is turned on at the third valley point (K=3) of resonant waveform 220.

In a quasi-resonant operation, the turn-on condition “valley of resonant voltage” can improve power efficiency, but limits the switching frequency of the flyback system. According to FIG. 2, the equation of power delivery P_(OUT) in one switching cycle of the converter is:

$P_{OUT} = {\frac{E_{Lm}}{T} = \frac{\frac{1}{2}L_{m}I_{peak}^{2}}{{\frac{V_{IN} + {NV}_{OUT}}{L_{m}} \times I_{peak}} + {\left( {K - \frac{1}{2}} \right)T_{QR}}}}$ $T = {{\frac{V_{IN} + {NV}_{OUT}}{L_{m}} \times I_{peak}} + {\left( {K - \frac{1}{2}} \right)T_{QR}}}$

where E_(Lm) is the energy stored in Lm, K is the valley count, and T_(QR) is an oscillation period of the resonant waveform. In one switching period T, the power convertor stores energy E_(Lm) into Lm during t_(ON) and delivers the E_(Lm) to output during t_(OFF). Thus, the average transferred power P_(OUT) is equal to the E_(Lm) over T. In the P_(OUT) equation, the only variable that can be modulated is the peak current I_(peak) because the valley count K should be a natural number. However, a power convertor should deliver Pour equal to the load that application is required. The I_(peak) has only one solution with a specific number K, and the switching period T is a constant value given by the couple of solution I_(peak) and K. As a result, any disturbance of I_(peak) for dithering switching period will be compensated by an external feedback loop and the switching frequency will converge to the given value which can fulfill the output load P_(OUT).

The invention teaches a control circuit for a quasi-resonant (QR) converter. As shown in the converter 100 shown in FIGS. 1, 2A, and 2B, for quasi-resonant operation, control circuit 150 includes a quasi-resonant controller 153 for turning on a power switch 101 at a valley point 222, 224, or 226, etc., of a resonant waveform 220 in a sensing signal DMEG during a discontinuous time t_(DIS) of the converter. The power switch is coupled to a primary winding 141 of the converter to control a primary switch, and the sensing signal DMEG monitoring the resonant waveform through an auxiliary winding 143. Control circuit 150 also includes a jitter controller 154 for adding a capacitance 130 in parallel to the power switch 101 at a peak point of the resonant waveform 220 in the sensing signal DMEG during the discontinuous time t_(DIS). For example, the capacitance can be added at peak points such as peak points 221, 223, or 225, etc. By varying the length of time during which the capacitance is coupled, the jitter controller 154 can vary the oscillation period T_(QR) of the resonant waveform to add a frequency jitter to the switching frequency of the converter.

FIG. 3 is a waveform diagram that illustrates a jitter operation in a quasi-resonant operation of the converter that embodies certain aspects of this invention. In FIG. 3, the following waveforms are shown over a switch cycle T of the converter, with reference to FIGS. 1, 2A, and 2B. The top waveform Vds shows the drain-to-source voltage “Vds” of the primary switch. The middle waveform “Drive” shows the control signal Drive applied to the primary switch 101. The bottom waveform “Mod” shows the control signal Mod applied to the modulation switch 131. A resonant waveform 220 exists in the waveforms of Vds during the discontinuous time. In the example of FIG. 3, resonant waveform 320 is shown to have three peak points 321, 323, and 325, and three valley points 322, 324, and 326, marked by K=1, K=2, and K=3. In the quasi-resonant operation, the quasi-resonant controller 153 in FIG. 1 turns on the power switch 101 at a valley point 326 of the resonant waveform in the sensing signal during the discontinuous time. In FIG. 3, the primary switch is turned on at the third valley point 326 (K=3) of resonant waveform 320, at the end of the switching period T of the switching cycle.

In FIG. 3, the control signal Mod turns on the modulation switch 131 for a time period t_(jitter). During the time period t_(jitter), modulation switch 131 is on, and modulation capacitor 130 is connected in parallel with primary switch 101, causing a modulation capacitor C_(sn) to be connected in parallel to the capacitance of the primary switch C_(oss). Accordingly, during the time period t_(jitter), the oscillation period for resonant waveform 320 is increased from T_(QR) to T_(QR1).

T _(QR)=2π√{square root over (L _(m) C _(oss))}

T _(QR1)=2π√{square root over (L _(m)(C _(oss) +C _(sn)))}

where L_(m) is the inductance of the primary winding, C_(oss) is the capacitance associated with the primary switch, and C_(sn) is the capacitance of the modulation capacitor. By varying the time period during which the modulation capacitor C_(sn) is connected, the period T of the switching cycle of the converter is also changed.

In order to reduce the hard switching loss as turning on MOS transistors, the modulation switch Q_(M) should be turned on at a peak point of Vds, and the primary switch Q_(L) should be turned on at a valley point of Vds. To fulfill the turn on timings, peak and valley detectors sense the DMEG node and produce pulse signals P_(Pulse) and V_(Pulse) based on the peaks and valleys of Vds sinusoid oscillation.

In order to introduce jitter into the switching cycle, the turn-on time t_(jitter) for modulation switch 131 is varied over time. FIGS. 4A-4D illustrate an example of varying the turn-on time t_(jitter) that embodies certain aspects of this invention. FIG. 4A shows that the time period t_(jitter), the modulation switch on-time, is varied in a linear manner between a minimum of 0 and a maximum of t_(jitterMax). FIG. 4B shows a corresponding switch frequency variation over a range of Δf. FIG. 4C shows a corresponding variation in the switch frequency waveform. FIG. 4D shows a spectrum plot of the Nth harmonic of the switch frequency waveform, with a center frequency of Nf_(avg). Even though the example in FIGS. 4A-4D illustrates a linear function for the jitter frequency, other time-varying functions can also be used.

The maximum range of the frequency spectrum is dependent on the valley count of the primary switch turn on and the value of modulation capacitor C_(sn). If the modulation switch Q_(M) turn-on signal is applied on the same valley count as the primary switch turn on, the dithering range of the total switching period will be only a half cycle of mixed LC resonant and can be expressed as follows.

${{\frac{1}{2}{\left( {T_{{QR}\; 1} - T_{QR}} \right).\Delta}\; T} \leq {\frac{1}{2}\left( {T_{{QR}\; 1} - T_{QR}} \right)}} = {{\pi \sqrt{L_{m}C_{OSS}}\left( {\sqrt{1 + \frac{C_{sn}}{C_{OSS}}} - 1} \right)\mspace{14mu} {for}\mspace{14mu} K_{jitter}} = {K_{QR}.}}$

FIGS. 5A and 5B illustrate the waveforms for the QR converter in which the jitter causes the oscillation period for the resonant waveform to vary. FIG. 5A illustrates the waveforms for the QR converter in which the jitter time t_(jitter) is nearly zero, and the oscillation period for resonant waveform is T_(QR), as described above. FIG. 5B illustrates the waveforms for the QR converter in which the jitter time t_(jitter) is at the maximum, t_(jitterMax), and the oscillation period for resonant waveform is T_(QR1), as described above.

FIGS. 6-10 are schematic or waveform diagrams illustrating the structures and functions of various components in the control circuit in a converter that embody certain aspects of this invention.

FIG. 6 shows schematic and waveform diagrams illustrating the structures and functions of a valley detector and a peak detector in the control circuit in a converter that embodies certain aspects of this invention. In FIG. 6, a valley detector 610 includes a first comparator 611 for comparing a sensing signal DMEG and a valley reference voltage Vref_V. A peak detector 620 includes a second comparator 622 for comparing a sensing signal DMEG and a peak reference voltage Vref_P. Waveform 630 illustrates the sensing signal DMEG, with the valley reference voltage Vref_V and peak reference voltage Vref_P. Waveform 640 illustrates the output waveform of the second comparator 622, showing a pulse signal P_(Pulse) where the sensing signal DMEG is greater than peak reference voltage Vref_P. Waveform 650 illustrates the output waveform of the first comparator 611, showing a pulse signal V_(Pulse) where the sensing signal DMEG is less than valley reference voltage Vref_V.

FIG. 7A is a simplified schematic diagram illustrating a jitter controller, and FIG. 7B illustrates a waveform diagram that describes the operation of the jitter controller that embodies certain aspects of this invention. As shown in FIGS. 7A and 7B, jitter controller 700 is an example of a jitter controller that can be used as jitter controller 154 in converter 100 in FIG. 1. Jitter controller 700 includes two D flipflops. A first D flipflop 710 has a first input terminal 711 for receiving a blanking time signal T_(FMAX), a second input terminal 712 for receiving the peak pulse signal P_(Pulse), a first output terminal 713 for providing a modulation-on signal Mod_On, and a second output terminal 714 for providing a complement of the modulation on signal. Jitter controller 700 also includes a jitter duration circuit 720 having a ramp signal circuit 721 with a current source 722 and capacitor 723 that starts charging the capacitor upon receiving the complement of the modulation on signal, from the second output terminal 714 of the first D flipflop 710, to produce a ramp signal RAMP. Jitter duration circuit 720 also has a comparator 725 for comparing the ramp signal RAMP and a jitter reference voltage V_(jitter) and providing a jitter stop signal 727. A second D flipflop 730 has a first input terminal 731 for receiving logic high signal Logic H, a second input terminal 732 for receiving the modulation on signal Mod_On from the first D flipflop 710, a reset terminal 735 for receiving the jitter stop signal 727, a first output terminal 733 for providing a modulation switch turn-on signal Mod, and a second output terminal 734 for providing a complement of the modulation switch turn-on signal. Jitter controller 700 also has an AND circuit 740 for receiving the modulation on signal Mod_On and the complement of the modulation switch turn-on signal Mod and providing a modulation switch turn-off signal Mod_Off. In FIG. 7B, TPON illustrates the on-time of the modulation switch.

FIG. 8A is a simplified schematic diagram illustrating a blanking time generation circuit, and FIG. 8B illustrates a waveform diagram that describes the operation of a blanking time generation circuit that embodies certain aspects of this invention. Similar to jitter duration circuit 720 in jitter controller 700, blanking time generation circuit 800 includes a ramp signal circuit 810 with a current source and capacitor that starts charging the capacitor upon receiving a Reset signal to produce a ramp signal. As shown in FIG. 8A, the Reset signal is a pulse signal produced by a rising edge one-shot circuit 820 at the rising edge of the primary switch Q_(L) turn-on signal. Blanking time generation circuit 800 also has a comparator 830 for comparing the ramp signal and a reference voltage V_(FMAX) and providing blanking time signal T_(FMAX). FIG. 8B shows the waveforms for the primary switch control signal Drive, blanking time signal T_(FMAX), and the Reset signal. Blanking time signal T_(FMAX) can be used to select the on-set of the modulation switch turn-on signal, as described above in connection with FIGS. 7A and 7B. It also limits the lower bound of the switching period.

FIG. 9 is a simplified schematic diagram illustrating a first example of a quasi-resonant controller that embodies certain aspects of this invention. FIG. 10 is a simplified schematic diagram illustrating a second example of a quasi-resonant controller that embodies certain aspects of this invention. As shown in FIGS. 9 and 10, quasi-resonant controllers 900 and 1000 are examples of quasi-resonant controllers that can be used as quasi-resonant controller 153 in converter 100 in FIG. 1. As shown in FIG. 9, quasi-resonant controller 900 has a first input terminal 901 for receiving the modulation switch turn-off signal, a second input terminal 902 for receiving the valley pulse signal V_(Pulse), and an output terminal 903 for providing a primary switch turn on signal Trigger. Similarly, as shown in FIG. 10, quasi-resonant controller 1000 has a first input terminal 1001 for receiving the modulation switch turn-off signal, a second input terminal 1002 for receiving the valley pulse signal V_(Pulse), and an output terminal 1003 for providing a primary switch turn on signal Trigger. Both quasi-resonant controller 900 and quasi-resonant controller 1000 provide a primary switch turn-on signal at a valley point of the resonant waveform in the discontinuous time.

As shown in FIG. 9, quasi-resonant controller 900 has a D flipflop 910 that includes a first input terminal 901 for receiving the modulation switch off signal Mod_Off, a second input terminal 902 for receiving the valley pulse signal V_(Pulse), and an output terminal 903 for providing the primary switch turn on signal Trigger. Waveform Mod illustrates the modulation switch turn-on signal. Waveform Mod_Off indicates that the modulation switch is turned off after the modulation switch has been on for a duration determined by the jitter control circuit. Waveform V_(Pulse) shows the valley pulse signals. D flipflop 910 produces the trigger signal Trigger at the rising edge of the first valley pulse signal V_(Pulse) after the modulation switch is turned off. The primary switch control signal Drive is provided by control circuit 150 in FIG. 1 in response to the Trigger signal. The turning on of primary switch indicates the beginning of a new switching cycle, and the D flipflop 910 receives a global signal Reset to standby for the new cycle.

As shown in FIG. 10, quasi-resonant controller 1000 has two D flipflops connected in series. A first D flipflop 1010 includes a first input terminal 1011 for receiving the modulation switch off signal Mod_Off, and a second input terminal 1012 for receiving the valley pulse signal V_(Pulse). A second D flipflop 1020 has a first input terminal 1021 for receiving an output signal from the first D flipflop 1010, and a second input terminal 1022 for receiving the valley pulse signal. The second D flipflop 1020 also has an output terminal 1023 for providing the primary switch trigger signal Trigger. FIG. 10 also shows waveforms that illustrate the same signals as those shown in FIG. 9. A difference between quasi-resonant controller 1000 and quasi-resonant controller 900 is that quasi-resonant controller 1000 includes two D flipflops, whereas quasi-resonant controller 900 has only one D flipflop. As a result, in quasi-resonant controller 1000, the primary switch is turned on at the second valley point after the modulation switch is turned off. The quasi-resonant controller 1000 makes the valley count different from the jitter peak count and the system switching frequency has a wider jitter range.

As described above, quasi-resonant controller 900 has one D flipflop, and quasi-resonant controller 1000 has two D flipflops connected in series. More generally, each quasi-resonant controller can have a flipflop chain having one D flipflip or two or more serially-connected D flipflops. A first one of the one or more D flipflops has a first input terminal for receiving the modulation switch off signal and a second input terminal for receiving the valley pulse signal. A last one of the one or more D flipflops has an output terminal for providing the primary switch trigger signal. Each D flipflop other than the first one of the one or more D flipflops has a first input terminal for receiving an output signal from a preceding D flipflop and a second input terminal for receiving the valley pulse signal. Even though the above examples include D flipflops, it is understood that similar functions can be implemented using other flipflops or latches that have two stable states and can be used to store state information.

FIG. 11A is a simplified schematic diagram illustrating a quasi-resonant (QR) converter with jitter that embodies certain aspects of this invention. FIG. 11B is a waveform diagram illustrating the operation of the quasi-resonant (QR) converter with the jitter of FIG. 11B that embodies certain aspects of this invention. FIG. 11A shows part of quasi-resonant (QR) converter 1100, which is similar to quasi-resonant (QR) converter 100 of FIG. 1, that illustrates that the modulation capacitor and the modulation switch are coupled with the primary switch in parallel between an input node of the power switch and a ground terminal. In this case, the power switch Q_(L) is an NMOS transistor and node 1101 is a drain node of the power switch. The modulation switch Q_(M) is a PMOS transistor, which has a source node 1103 coupled to the ground node GND. In this case, the modulation switch Q_(M) is also referred to as a low-side PMOS. FIG. 11B shows that the modulation switch is turned on at the first peak 1111 of the resonant waveform in the discontinuous time, and the primary switch is turned on at the third valley 1113 of the resonant waveform in the discontinuous time. As described above, during the time when the modulation switch is turned on, the modulation capacitor is connected, and the oscillation period of the resonant waveform is T_(QR1). When the modulation switch is turned off, the modulation capacitor is disconnected, and the oscillation period of the resonant waveform is T_(QR). Accordingly, with a time-varying duration of T_(QR1), a jitter is added to the quasi-resonant converter.

FIG. 12A is a simplified schematic diagram illustrating a quasi-resonant (QR) converter with jitter that embodies certain aspects of this invention. FIG. 12B is a waveform diagram illustrating the operation of the quasi-resonant (QR) converter with the jitter of FIG. 12A that embodies certain aspects of this invention. FIG. 12A shows part of quasi-resonant (QR) converter 1200, which is similar to quasi-resonant (QR) converter 100 of FIG. 1, except that the modulation capacitor and the modulation switch are coupled with the primary switch in parallel between an input node of the power switch and a power terminal. In this case, the power switch Q_(L) is an NMOS transistor and node 1201 is a drain node of the power switch. The modulation switch Q_(M) is an NMOS transistor, which has a drain node 1203 coupled to a power node in series with the modulation capacitor, in this case, V_(in). In this case, the modulation switch Q_(M) is also referred to as a high-side NMOS. The NMOS Q_(M) needs a bootstrap driving circuit to provide a control signal for the swinging source voltage. Node SW provides a reference ground for the control signal.

The operation of quasi-resonant (QR) converter 1200 in FIG. 12B is similar to the operation of quasi-resonant (QR) converter 1100 in FIG. 11B. As shown in FIG. 12B, the modulation switch is turned on at the first peak 1211 of the resonant waveform in the discontinuous time, and the primary switch is turned on at the third valley 1213 of the resonant waveform in the discontinuous time. Similar to above, during the time when the modulation switch is turned on, the oscillation period of the resonant waveform is T_(QR1). When the modulation switch is turned off, the oscillation period of the resonant waveform is T_(QR). Accordingly, a jitter is added to the quasi-resonant converter.

FIG. 13 is a simplified flowchart that illustrates a method for controlling a quasi-resonant (QR) converter that embodies certain aspects of this invention. As shown in FIG. 13, method 1300 includes, at 1310, identifying valley points and peak points of a resonant waveform in a sensing signal during a discontinuous time of the converter. Method 1300 also includes, at 1320, turning on a modulation switch to add a capacitance in parallel to the power switch at a peak point of the resonant waveform in the sensing signal during the discontinuous time, to vary an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the converter. Method 1300 also includes, at 1330, turning on a power switch at a valley point of a resonant waveform in a sensing signal after the modulation switch has been turned off. The power switch is coupled to a primary winding of the converter to control a primary current flow, and the sensing signal is representative of the resonant waveform.

In method 1300, adding a capacitance in parallel to the power switch can include turning on a modulation switch that is coupled in series with a modulation capacitor. Method 1300 also includes turning on the modulation switch at a first peak point in the resonant waveform after a blanking time, and turning off the modulation switch after a time period based on a time-varying function to vary a turn-on time of the modulation switch. The method can also include turning on the power switch at a valley point of the resonant waveform after a preset off time of the modulation switch.

FIG. 14 is a simplified schematic diagram illustrating a power converter with jitter that embodies certain aspects of this invention. FIG. 14 shows part of a power converter 1400, which is similar to flyback converter 100 of FIG. 1, including the inductance L_(m) of the primary winding and auxiliary winding AUX providing VCC. In this example, a modulation capacitor C_(SN) is shunted with parasitic capacitor C_(OSS) to change the resonant period and modulation switch Q_(M) is in series with C_(SN) to control the shunted time t_(jitter).

FIG. 15 illustrates the waveforms for the power converter of FIG. 14 that embodies certain aspects of this invention. FIG. 15 plots the Drive signal that turns on the power switch Q_(L), the Mod signal that turns on the modulation switch Q_(M), and the drain-source voltage V_(DS) of the power switch Q_(L). As shown in FIG. 15, the switching period of the flyback system can be varied by different t_(jitter) which changes the quasi-resonant oscillation period from T_(QR) to T_(QR1), where, as described above in connection with FIGS. 5A and 5B, T_(QR)=2π√{square root over (L_(m)C_(oss))} is the oscillation period of resonant waveform with modulation switch Q_(M) turned off, and T_(QR1)=2π√{square root over (L_(m)(C_(OSS)+C_(sn)))} is the oscillation period of resonant waveform with modulation switch Q_(M) turned on.

By linearly changing the t_(jitter), the switching frequency of the converter can be spread out in a frequency range as shown in FIG. 16, similar to that described above in connection with FIGS. 4A-4D. The benefits of spectrum separating for electro-magnetic interference (EMI) and quasi-resonant control for C_(OSS) switching loss can be achieved at the same time. However, the inventor has recognized that the switching loss of the power converter can be further improved. For example, the C_(OSS) switching loss can still be large with high input voltage V_(IN).

FIG. 17 plots the Drive signal that turns on the power switch Q_(L), the Mod signal that turns on the modulation switch Q_(M), the drain-source voltage V_(DS) of the power switch Q_(L), and the current I_(m) in the primary winding L_(m). As shown in FIG. 17, the C_(SN) changes the resonant period, but keeps the resonant amplitude the same at the boundary of frequency modulation region. As a result, the switching loss is still similar to the traditional quasi-resonant control, and the flyback system can have lower efficiency with high input AC voltage.

This invention further teaches a technique to reduce the switching loss of C_(OSS) associated with the power switch for the power converter. In an example, in order to reduce the switching loss of the power switch C_(OSS), the inductor current I_(m) flowing into input voltage source V_(IN) is to be kept in inductor L_(m) at the end of the modulation switch Q_(M) modulation time.

FIG. 18 shows an example of generating the negative inductor current I_(M). FIG. 18 plots the Drive signal that turns on the power switch Q_(L), the Mod signal that turns on the modulation switch Q_(M), the drain-source voltage V_(DS) of the power switch Q_(L), and the current I_(m) in the primary winding L_(m). In an example, a large C_(SN) is selected to have T_(QR1)>>t_(jitter_MAX), and the modulation time of Q_(M) includes a dithering t_(jitter)(t) variant with time and an offset T(V_(IN)) controlled by input voltage V_(IN). In other words, the frequency jitter includes a first portion that varies with the input voltage of the power converter and a second portion that is a time-varying function. With a high V_(IN), the large T(V_(IN)) causes the L_(m) to have a large negative I_(m) as soon as the Q_(M) is turned off. This initial current increases the amplitude of the following quasi-resonant waveform and reduces the valley switching voltage on C_(OSS).

FIGS. 19A-19C plot the Mod signal that turns on the modulation switch Q_(M), the drain-source voltage V_(DS) of the power switch Q_(L), and the current I_(m) in the primary winding L_(m) at different input voltages V_(IN). FIG. 19A shows the waveforms at a high V_(IN), FIG. 19B shows the waveforms at a medium V_(IN), and FIG. 19C shows the waveforms at a low V_(IN). With smaller input voltage V_(IN), the smaller T(V_(IN)) can induce less I_(m) and less resonant amplitude to adapt to less Q_(L)-V_(DS) on capacitance C_(OSS).

FIG. 20 shows the example of generating the negative I_(m) at low V_(IN). Similar to FIG. 18, FIG. 20 plots the Drive signal that turns on the power switch Q_(L), the Mod signal that turns on the modulation switch Q_(M), the drain-source voltage V_(DS) of the power switch Q_(L), and the current I_(m) in the primary winding L_(m). However, in FIG. 20, the V_(IN) is relatively low, and T(V_(IN)) is small so the modulation switch Q_(M) is turned off earlier. It induces less negative I_(m) and less quasi-resonant amplitude subsequently, which is suitable for the low V_(IN) since the resonant waveform already have low V_(DS) drop at the valley point.

FIG. 21 is a simplified schematic diagram of a power converter that embodies certain aspects of this invention. Power converter 2100 includes many components similar to those in converter 100 of FIG. 1, as described in detailed below. However, in power converter 2100, an input voltage magnitude detector 2160 is added to provide a signal f(V_(IN)) to the jitter controller 2154 to provide a frequency jitter that includes a first portion that varies with the input voltage of the power converter and a second portion that is a time-varying function. The switching loss of the power transistor is reduced and power efficiency can be improved.

Power converter 2100 includes a transformer 2102, which includes a primary winding 2141 for coupling to an input voltage V_(IN) and a secondary winding 2142 for providing the output voltage V_(OUT) through a rectifying diode 2120 and a capacitor 2119. A current in the rectifying diode is I_(D). Transformer 2102 also has an auxiliary winding 2143 for providing a sensing signal DMEG monitoring a resonant waveform of the converter during a discontinuous time. Auxiliary winding 2143 also provides a voltage V_(CC), which can be used as a power supply for the support circuitry, such as a control circuit. In FIG. 21, Vp denotes the voltage at the primary winding, Vs denotes the voltage at the secondary winding, and Va denotes the voltage at the auxiliary winding. In FIG. 21, L_(m) represents the inductance of the primary winding, and N represents the ratio of coil turns in the primary winding to the secondary winding. C_(oss) represents the capacitance associated with primary switch 2101, including the capacitance from the body diode. Vds represents the drain-source voltage across the primary switch.

Converter 2100 includes a control circuit 2150. Converter 2100 also includes a power switch 2101 (also designated as Q_(L)) coupled to primary winding 2141 and control circuit 2150 for receiving a control signal to turn on and off power switch 2101 to control the primary current through primary winding 2141 in order to regulate output voltage V_(OUT). In FIG. 21, power switch 2101 is shown as a MOSFET power transistor. In the embodiment of FIG. 21, control circuit 2150 can receive its operating power from V_(cc) provided by the auxiliary winding. Control circuit 2150 can also receive sensing signal DMEG from auxiliary winding 2143. Control circuit 2150 can also receive a current sense signal representative of the primary current through a current sense resistor with a resistance (as shown in FIG. 1, but not shown in FIG. 21). Control circuit 2150 provides a control signal Drive to control power switch 2101. Control circuit 2150 turns on the power switch 2101 based on information provided by the sensing signal DMEG and turns off the power 2101 based on information provided by the current sense signal Vcs.

As shown in FIG. 21, converter 2100 also has a modulation capacitor 2130 (also designated as C_(SN)) and a modulation switch 2131 (also designated as Q_(M)) coupled in parallel to power switch 2101. In this arrangement, modulation switch 2131 is coupled in series with capacitor 2130. Control circuit 2150 includes a valley detector 2151 for detecting valley points in the resonant waveform in the sensing signal DMEG during the discontinuous time of converter 2100. Control circuit 2150 also includes a peak detector 2152 for detecting peak points in the resonant waveform in the sensing signal during the discontinuous time. Control circuit 2150 also includes a power controller 2153 for turning on the power switch 2101 at a valley point of a resonant waveform in the sensing signal during a discontinuous time. Control circuit 2150 further includes a jitter controller 2154 for turning on the modulation switch 2131 at a peak point of the resonant waveform in the sensing signal during the discontinuous time. Control circuit 2150 also includes an oscillator OSC 2155, which provides a T_(FMAX) signal to jitter controller 2154. In addition to the T_(FMAX) signal, jitter controller 2154 also receives a Ppulse signal from peak detector 2152, and provides a Mod_Off signal to power controller 2153. Power controller 2153 also receives a Vpulse signal from valley detector 2151. Control circuit 2150 also includes a flipflop 2156 that outputs the Drive signal.

As explained in detail below, jitter controller 2154 varies a turn-on time of the modulation switch 2131 to add a frequency jitter to the switching frequency of the converter. The waveform of Vds is mirrored to the auxiliary winding and detected by a peak detector and a valley detector. The jitter controller determines the target peak count to turn on Q_(M) and linearly modulates the on time of Q_(M). After Q_(M) is turned off, the power controller is enabled by the jitter controller to wait for proper valley count and turn on Q_(L) at the valley of Vds.

Power converter 2100 also includes an input voltage magnitude detector 2160 to provide a signal f(V_(IN)) to the jitter controller 2154 to provide a frequency jitter that includes a first portion that varies with the input voltage of the power converter and a second portion that is a time-varying function. In the example of FIG. 21, the input voltage magnitude detector 2160 includes a sample-and-hold block (V_(IN) S/H) to sense the V_(IN) information through the DMEG node during the on-time of Q_(L). The sampled f(V_(IN)) is used to add a variable of Q_(M) modulation time which is T(V_(IN))+t_(jitter)(t). In an example, the controller turns on the Q_(M) at a peak of V_(ds) and turns off Q_(M) according to the Q_(M) modulation time. After the Q_(M) is turned off, the V_(ds) falls rapidly due to the increasing amplitude of quasi-resonant waveform. Thus the valley detector sends a signal to turn on Q_(L) and a new switching cycle begins.

FIG. 22 shows schematic and waveform diagrams illustrating the structures and functions of a valley detector and a peak detector in the control circuit in a converter that embodies certain aspects of this invention. In FIG. 22, a valley detector 2210 includes a first comparator 2211 for comparing a sensing signal DMEG and a valley reference voltage Vref_V. A peak detector 2220 includes a second comparator 2222 for comparing a sensing signal DMEG and a peak reference voltage Vref_P. Waveform 2230 illustrates the sensing signal DMEG, with the valley reference voltage Vref_V and peak reference voltage Vref_P. Waveform 2240 illustrates the output waveform of the second comparator 2222, showing a pulse signal P_(Pulse) where the sensing signal DMEG is greater than peak reference voltage Vref_P. Waveform 2250 illustrates the output waveform of the first comparator 2211, showing a pulse signal V_(Pulse) where the sensing signal DMEG is less than valley reference voltage Vref_V. This example detects peaks and valleys of V_(ds) through the DMEG voltage. The rising edge of P_(Pulse) and V_(Pulse) are sent to turn on Q_(M) at peak of V_(ds) and turn on Q_(L) at valley of V_(ds).

FIG. 23 shows a schematic for an input voltage magnitude detector 2300, which can be used as input voltage magnitude detector 2160 in control circuit 2150 in FIG. 21. As shown in FIG. 23, input voltage magnitude detector 2300 includes an inverting amplifier 2310 and a sample-and-hold block 2320 to sense the V_(IN) information through the DMEG node during the on-time of Q_(L). During the on-time of Q_(L), the V_(IN) is applied on the primary side of transformer to store energy into inductor L_(m), and the auxiliary winding induces a negative voltage proportional to V_(IN) according to the turn ratio. With the inverting amplifier, the V_(IN) information on DMEG node is converted into a signal which is a function of V_(IN), and a sample and hold circuit is applied to keep the signal measured during the Q_(L) on time. The sampled signal f(V_(IN)) is used to add a variable of Q_(M) modulation time which is T(V_(IN))+t_(jitter)(t). Inverting amplifier 2310 is coupled to a reference signal V_(OS). A switch in the ample-and-hold block 2320 is controlled by the Drive signal. FIG. 23 also plots the Drive signal that turns on the power switch Q_(L), the DMEG signal, which has a negative amplitude proportional to V_(IN) during the Q_(L) on time, and the output f(V_(IN)) of the input voltage magnitude detector 2300.

FIG. 24 is a simplified schematic diagram illustrating a jitter controller, and FIG. 25 illustrates a waveform diagram that describes the operation of the jitter controller that embodies certain aspects of this invention. As shown in FIGS. 24 and 25, jitter controller 2400 is an example of a jitter controller that can be used as jitter controller 2154 in converter 2100 in FIG. 21. Jitter controller 2400 includes two D flipflops. A first D flipflop 2410 has a first input terminal 2411 for receiving a blanking time signal T_(FMAX), a second input terminal 2412 for receiving the peak pulse signal P_(Pulse), a first output terminal 2413 for providing a modulation-on signal Mod_On, and a second output terminal 2414 for providing a complement of the modulation on signal.

Jitter controller 2400 also includes a jitter duration circuit 2420 having a first ramp signal circuit 2421 with a current source 2422 and capacitor 2423 that starts charging the capacitor upon receiving the complement of the modulation on signal, from the second output terminal 2414 of the first D flipflop 2410, to produce a first ramp signal V_(RAMP1). Jitter duration circuit 2420 also has a first comparator 2425 for comparing the first ramp signal V_(RAMP1) and an input voltage reference voltage f(V_(IN)) and providing a jitter offset signal 2427.

Jitter duration circuit 2420 also has a second ramp signal circuit 2451 with a current source 2452 and capacitor 2453 that starts charging the capacitor upon receiving jitter offset signal 2427 through an inverter 2428 to produce a second ramp signal V_(RAMP2). Jitter duration circuit 2420 also has a comparator 2455 for comparing the second ramp signal V_(RAMP2) and a time-varying jitter reference voltage V_(jitter)(t) and providing a jitter stop signal 2457.

In FIG. 24, a second D flipflop 2430 has a first input terminal 2431 for receiving logic high signal Logic H, a second input terminal 2432 for receiving the modulation on signal Mod_On from the first D flipflop 2410, a reset terminal 2435 for receiving the jitter stop signal 2457, a first output terminal 2433 for providing a modulation switch turn-on signal Mod, and a second output terminal 2434 for providing a complement of the modulation switch turn-on signal. Jitter controller 2400 also has an AND circuit 2440 for receiving the modulation on signal Mod_On and the complement of the modulation switch turn-on signal Mod and providing a modulation switch turn-off signal Mod_Off.

FIG. 25 shows example waveforms of jitter controller 2500, also referred to as the modulation time controller. FIG. 25 plots the Drive, T_(FMAX), P_(Pulse), V_(RAMP1), V_(RAMP2), Mod, Mod_Off, and Reset signals. As shown in FIG. 25, the beginning of the modulation time is triggered by the first P_(Pulse) signal after a blanking time signal T_(FMAX) goes high. The T_(FMAX) signal in FIG. 25 is generated by a timer shown in FIG. 26 to limit the maximum value of the system switching frequency, and the P_(Pulse) is signal from the peak detector to turn on Q_(M) with less switching loss. As described above in connection with FIG. 24, the length of modulation time MOD is determined by two timers in series. The first timer generates a delay T(V_(IN)) according to the signal f(V_(IN)), and the second timer generates another delay t_(jitter)(t) according to a time variant signal V_(jitter)(t). The summation of the two delays determines a signal Mod to drive Q_(M) and achieves the modulation time with time variant dithering and V_(IN) controlled offset. In some embodiments, the time-varying signal can be provided by an oscillator, for example.

After the Q_(M) turn off, the modulation time controller enables a Mod_Off flag. Since the offset of modulation time of Q_(M) increases the resonant amplitude of V_(ds), the Q_(L) should be turned on at the first valley after the modulation time to have lower switching loss.

FIG. 26 shows a simplified schematic diagram illustrating a blanking time generation circuit and a waveform diagram that describes the operation of timer circuit 2600 that can be used as a blanking time generation circuit that embodies certain aspects of this invention. Timer circuit 2600 includes a ramp signal circuit 2610 with a current source and capacitor that starts charging the capacitor upon receiving a Reset signal to produce a ramp signal. As shown in FIG. 26, the Reset signal is a pulse signal produced by a rising edge one-shot circuit 2620 at the rising edge of the primary switch Q_(L) turn-on signal. Blanking time generation circuit 2600 also has a comparator 2630 for comparing the ramp signal and a reference voltage V_(FMAX) and providing blanking time signal T_(FMAX). FIG. 26 also shows the waveforms for the primary switch control signal Drive, blanking time signal T_(FMAX), and the Reset signal. Blanking time signal T_(FMAX) can be used to select the on-set of the modulation switch turn-on signal, as described above in connection with FIGS. 24 and 25. It also limits the lower bound of the switching period.

FIG. 27 is a simplified schematic diagram illustrating a first example of a power controller that embodies certain aspects of this invention. As shown in FIG. 27, power controller 2700 is an example of power controller that can be used as power controller 2153 in converter 2100 in FIG. 21. As shown in FIG. 27, power controller 2700 has a first input terminal 2701 for receiving the modulation switch turn-off signal Mod_Off, a second input terminal 2702 for receiving the valley pulse signal V_(Pulse), and an output terminal 2703 for providing a primary switch turn on signal Trigger. Power controller 2700 provides a primary switch turn-on signal at a valley point of the resonant waveform in the discontinuous time.

As shown in FIG. 27, power controller 2700 has a D flipflop 2710 that includes a first input terminal 2701 for receiving the modulation switch off signal Mod_Off, a second input terminal 2702 for receiving the valley pulse signal V_(Pulse), and an output terminal 2703 for providing the primary switch turn on signal Trigger. Waveform Mod illustrates the modulation switch turn-on signal. Waveform Mod_Off indicates that the modulation switch is turned off after the modulation switch has been on for a duration determined by the jitter control circuit. Waveform V_(Pulse) shows the valley pulse signals. D flipflop 2710 produces the trigger signal Trigger at the rising edge of the first valley pulse signal V_(Pulse) after the modulation switch is turned off. The primary switch control signal Drive is provided by control circuit 2150 in FIG. 21 in response to the Trigger signal. Turning on the primary switch indicates the beginning of a new switching cycle, and the D flipflop 2710 receives a global signal Reset to standby for the new cycle. The power controller sends the trigger signal with the first V_(Pulse) after the Mod_Off flag is enabled. The trigger signal turns on Q_(L) and begins the next switching cycle of system.

FIG. 28 is a simplified flowchart that illustrates a method for controlling a power converter that embodies certain aspects of this invention. As shown in FIG. 28, method 2800 includes, at 2810, turning on a power switch in response to a resonant waveform in a sensing signal during a discontinuous time of the power converter. Method 2800 also includes, at 2820, adding a capacitance in parallel to the power switch during the discontinuous time, to vary an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the power converter.

Examples of power converters implementing method 2800 are described above in connection with FIGS. 14-27. In some embodiments, the frequency jitter can include a first portion that varies with an input voltage of the power converter and a second portion that is a time-varying function. In method 2800, adding a capacitance in parallel to the power switch can include turning on a modulation switch that is coupled in series with a modulation capacitor. Method 2800 can also include turning on a power switch in response to a resonant waveform in a sensing signal during a discontinuous time of the power converter, wherein the power switch is coupled to a primary winding of the power converter to control a primary current flow. The method can also include adding a capacitance in parallel to the power switch during the discontinuous time, to vary an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the power converter. The method can add a capacitance in parallel to the power switch by turning on a modulation switch that is coupled in series with a capacitor, wherein the capacitor and the modulation switch are coupled in parallel with the power switch. The frequency jitter can include a first portion that varies with an input voltage of the power converter and a second portion that is a time-varying function. 

What is claimed is:
 1. A power converter, comprising: a transformer having a primary winding for coupling to an input voltage, a secondary winding providing an output voltage of the power converter, and a sensing circuit for providing a sensing signal, which monitors a resonant waveform of the power converter during discontinuous time; a power switch for coupling to the primary winding of the power converter to control a primary current flow; a capacitor and a modulation switch coupled in parallel to the power switch, the modulation switch being coupled in series with the capacitor; and a control circuit, comprising: a power controller for turning on the power switch in response to the resonant waveform in the sensing signal during a discontinuous time; and a jitter controller for turning on the modulation switch in response to the resonant waveform in the sensing signal during the discontinuous time, wherein the jitter controller varies a turn-on time of the modulation switch to add a frequency jitter to a switching frequency of the power converter.
 2. The power converter of claim 1, wherein the control circuit further comprises: a valley detector for detecting valley points in the resonant waveform in the sensing signal during the discontinuous time; and a peak detector for detecting peak points in the resonant waveform in the sensing signal during the discontinuous time.
 3. The power converter of claim 2, wherein the jitter controller is configured to: turn on the modulation switch at a first peak point in the resonant waveform after a blanking time; and turn off the modulation switch after a time period based on a time-varying function to vary the turn-on time of the modulation switch.
 4. The power converter of claim 2, wherein the control circuit further comprises an input voltage magnitude detector.
 5. The power converter of claim 4, wherein the jitter controller is coupled to the valley detector, the peak detector, and the input voltage magnitude detector to provide a frequency jitter that includes a first portion that varies with the input voltage of the power converter and a second portion that is a time-varying function.
 6. The power converter of claim 3, wherein the turn-on time of the modulation switch comprises a periodic function of linearly varying time.
 7. The power converter of claim 3, wherein the blanking time is based on a selectable reference voltage.
 8. The power converter of claim 3, wherein the power controller is configured to turn on the power switch at a valley point of the resonant waveform after a preset off time of the modulation switch.
 9. The power converter of claim 8, wherein the power controller is configured to turn off the power switch based on a constant on-time, a feedback signal, or a peak primary current sense signal.
 10. A control circuit for a power converter, comprising: a power controller for turning on a power switch in response to a resonant waveform in a sensing signal during a discontinuous time of the power converter, wherein the power switch is coupled to a primary winding of the power converter to control a primary current flow, and the sensing signal monitors the resonant waveform of the power converter through an auxiliary winding; and a jitter controller for adding a capacitance in parallel to the power switch in response to the resonant waveform in the sensing signal during the discontinuous time, wherein the jitter controller varies an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the power converter.
 11. The control circuit of claim 10, wherein the jitter controller is configured to turn on a modulation switch that is coupled in series with a capacitor, and wherein the capacitor and the modulation switch are coupled in parallel with the power switch.
 12. The control circuit of claim 11, wherein the control circuit further comprises: a valley detector for providing valley pulse signals at valley points in the resonant waveform in the sensing signal during the discontinuous time; and a peak detector for providing peak pulse signals at peak points in the resonant waveform in the sensing signal during the discontinuous time.
 13. The control circuit of claim 12, wherein the control circuit further comprises an input voltage magnitude detector.
 14. The control circuit of claim 13, wherein the jitter controller is coupled to the valley detector, the peak detector, and the input voltage magnitude detector to provide a frequency jitter that includes a first portion that varies with the input voltage of the power converter and a second portion that is a time-varying function.
 15. The control circuit of claim 14, wherein the jitter controller comprises: a first ramp signal circuit that responds to a signal from the input voltage magnitude detector to provide the first portion of the frequency jitter; and a second ramp signal circuit that responds to a time-varying signal to provide the second portion of the frequency jitter.
 16. The control circuit of claim 12, wherein the jitter controller is configured to: turn on the modulation switch at a first peak point in the resonant waveform after a blanking time; and turn off the modulation switch after a time period in response to the frequency jitter provided by the jitter controller to vary a turn-on time of the modulation switch.
 17. A method for controlling a power converter, comprising: turning on a power switch in response to a resonant waveform in a sensing signal during a discontinuous time of the power converter, wherein the power switch is coupled to a primary winding of the power converter to control a primary current flow; and adding a capacitance in parallel to the power switch during the discontinuous time, to vary an oscillation period of the resonant waveform to add a frequency jitter to a switching frequency of the power converter.
 18. The method of claim 17, wherein adding a capacitance in parallel to the power switch comprises turning on a modulation switch that is coupled in series with a capacitor, wherein the capacitor and the modulation switch are coupled in parallel with the power switch.
 19. The method of claim 18, wherein the frequency jitter comprises a first portion that varies with an input voltage of the power converter and a second portion that is a time-varying function.
 20. The method of claim 18, further comprising: providing valley pulse signals at valley points in the resonant waveform in the sensing signal during the discontinuous time; providing peak pulse signals at peak points in the resonant waveform in the sensing signal during the discontinuous time; and providing a signal representing the magnitude of an input voltage. 